搜索资源列表
PROGRAMMING
- 怎么编程设计好CPLD,外文资料,对学CPLD/FPGA的人应该有帮助的-Programming how good CPLD, foreign language materials, learning CPLD/FPGA of the people should be helpful
CPLDFPGA
- 怎么编程设计好CPLD,外文资料,对学CPLD/FPGA的人应该有帮助的-Programming how good CPLD, foreign language materials, learning CPLD/FPGA of the people should be helpful
CPLD-radom
- 基于C P L D 的伪随机序列发生器,用FPGA产生随机序列的-CPLD-based pseudo-random sequence generator, generate random sequences using FPGA
FPGA_CPLD
- FPGA CPLD入门教程 对于初学者很实用-FPGA CPLD Getting Started tutorial is very useful for beginners
ccd-nios
- 提出一种面阵CCD的驱动和数据采集系统的设计方案,采用了nios和cpld的组合。-Presents a planar array CCD drive and data acquisition system design, using a combination of nios and cpld
s3esk_startup
- 利用kcpsm3控制lcd显示 平台:ise 10.1, picoblaze, Spartan3e 开发板 说明:综合按键和lcd、led的功能,思想简单,需要新技术,适合想在fpga方面深造的人。-using kcpsm3 for lcd display platform: ise 10.1, picoblaze, Spartan-3E FPGA Starter Kit Board comment: involve lcd/led/switch, simple mind bu
PIC10_RISC_Verilog
- The PIC10-compatible microcontroller core was implemented as part of a client project where a small PIC-compatible microprocessor IP Core was needed to be integrated into a CPLD or FPGA. This allowed extremely fast but yet simple firmware programming
Verilog
- VERILOG语言的学习,更好的运用CPLD,FPGA-VERILOG language learning, better use of CPLD, FPGA
Design_Recipes_for_FPGAs
- FPGA & CPLD eBook. Very good, must read.
vhdl_sram_ctrl
- Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
fpgacpld
- FPGA/CPLD开发教程,可以作为入门级学习资料。-The PDF file of CPLD,
vhdl-TAXI
- 随着EDA技术的发展及大规模可编程逻辑器件CPLD/FPGA的出现,电子系统的设计技术和工具发生了巨大的变化,通过EDA技术对CPLD/FPGA编程开发产品,不仅成本低、周期短、可靠性高,而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统,使其实现汽车启动、停止、暂停时计费以及预置等功能,通过设置计数电路进行路费及路程的计数,通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示,通过设计快速扫描电路显示车费及路费,突出了其作为硬件描述语言的良好的可读性的优点。通
STOPWATCH
- 是基于FPGA/CPLD的跑表程序,可以存储记录多个运动员的跑步时间,是利用VHDL语言编写的,可以有助于学习EDA技术,可以参考学习,可以帮助你完成VHDL语言的课程设计。-Is based on FPGA/CPLD s stopwatch program, many athletes can store records of running time, is the use of VHDL language, and can help to learn EDA, can refer to t
VHDLbaseddesignofmusicplayer
- 在EDA开发工具Quartus II 6.0平台上,采用VHDL语言层次化和模块化的设计方法,通过音符编码的设计思想,预先定制乐曲,实现动态显示乐曲演奏电路的设计,并在此基础上,基于同一原理,使此电路同时具备了简易电子琴的功能,使基于CPLD/FPGA芯片的乐曲播放数字电路得到了更好的优化,提高了设计的灵活性和可扩展性。- Based on the QuartusII-the EDA development tool, this design has adopted the method of
51fpga
- 51单片机 IP核 FPGA CPLD 基于EDA技术的兼容MCS_51单片机IP核设计- FPGA CPLD
FPGAclock
- FPGA CPLD重要设计思想及工程应用时钟设计-FPGA CPLD design and engineering major clock design
dac8552
- 使用Verilog HDL语言编写的实现DAC8552的时序程序,单片机总线与CPLD/FPGA通信,单片机负责控制送数实现功能。-Use Verilog HDL language DAC8552 realization of temporal procedures, SCM bus and CPLD/FPGA communication, SCM control to send several functions.
FPGA_Verilog_LCD_12864
- 使用Verilog HDL语言编写的驱动LCD12864的时序,可以直接用FPGA/CPLD驱动LCD12864了。-Using Verilog HDL language driver LCD12864 timing, can be directly used FPGA/CPLD driver LCD12864 the.
CPLD
- FPGA与CPLD之间通过串口通信的程序,波特率为9600。-FPGA and CPLD via the serial port communication program, the baud rate to 9600.
modesim
- 讲述使用modelsim进行验证,使用verilogHDL语言进行建模。其中还包括一个讲述怎样用verilog语言编写测试台的详细文档,对fpga cpld设计的后期验证有很大的帮助。-About the use modelsim for authentication, use verilogHDL language modeling. It also includes a focus on how to use verilog test bench written a detailed doc